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Advanced Information
CAT512
8-Bit Dual Digital POT with Independent Reference Inputs FEATURES
s Output settings retained without power s Independent Reference Inputs s Output range includes both supply rails s Programming voltage generated on-chip s 2 independently addressable outputs s Serial P interface s Single supply operation: 2.7V-5.5V
APPLICATIONS
s Automated product calibration. s Remote control adjustment of equipment s Offset, gain and zero adjustments in Self-
Calibrating and Adaptive Control systems.
s Tamper-proof calibrations.
DESCRIPTION
The CAT512 is a dual 8-Bit Memory DAC designed as an electronic replacement for mechanical potentiometers and trim pots. Intended for final calibration of products such as camcorders, fax machines and cellular telephones on automated high volume production lines and systems capable of self calibration, it is also well suited for applications were equipment requiring periodic adjustment is either difficult to access or located in a hazardous environment. The CAT512 offers 2 independently programmable DACs each having its own reference inputs and each capable of rail to rail output swing. Output settings, stored nonvolatile EEPROM memory, are not lost when the device is powered down and are automatically reinstated when power is returned. Each output can be dithered to test new output values without effecting the stored settings and stored settings can be read back without disturbing the DAC's output. FUNCTIONAL DIAGRAM
VDD
Control of the CAT512 is accomplished with a simple 3 wire serial interface. A Chip Select pin allows several CAT512's to share a common serial interface and communications back to the host controller is via a single serial data line thanks to the CAT512's Tri-Stated Data Output pin. A RDY/BSYoutput working in concert with an internal low voltage detector signals proper operation of EEPROM Erase/Write cycle. The CAT512 operates from a single 3-5 volt power supply. The high voltage required for EEPROM Erase/ Write operations is generated on-chip. The CAT512 is available in the 0C to 70C Commercial and -40C to +85C Industrial operating temperature ranges and offered in 14-pin plastic DIP and Surface mount packages.
PIN CONFIGURATION
1
RDY/BSY
3
SERIAL DATA OUTPUT
6
DIP Package (P)
DO
SOIC Package (J)
VDD CLK RDY/BSY CS DI DO PROG 1 2 3 4 5 6 7 14 13 12 11 CAT512 10 9 8 VREF H1 VREF H2 VOUT1 VOUT2 VREF L2 VREF L1 GND
PROG
7
PROGRAM CONTROL 14 EEPROM LATCH
DAC 1 V REF H1
VDD CLK
1 V OUT V REF L1
1 2 3 4 5 6 7
14 13 12 11 CAT512 10 9 8
VREF H1 VREF H2 VOUT1 VOUT2 VREF L2 VREF L1 GND
12 9
CLK
2 DATA CONTROLLER 13
RDY/BSY CS
CS
4
DI
5 EEPROM LATCH
DAC 2
V H2 REF V 2 OUT VREF L2
DI DO PROG
11 10
H.V. CHARGE PUMP
CAT512
8 GND
(c) 2000 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
1
CAT512
ABSOLUTE MAXIMUM RATINGS Supply Voltage* VDD to GND ...................................... -0.5V to +7V Inputs CLK to GND ............................ -0.5V to VDD +0.5V CS to GND .............................. -0.5V to VDD +0.5V DI to GND ............................... -0.5V to VDD +0.5V RDY/BSY to GND ................... -0.5V to VDD +0.5V PROG to GND ........................ -0.5V to VDD +0.5V VREFH to GND ........................ -0.5V to VDD +0.5V VREFL to GND ......................... -0.5V to VDD +0.5V Outputs D0 to GND ............................... -0.5V to VDD +0.5V VOUT 1- 2 to GND ................... -0.5V to VDD +0.5V
Advanced Information Operating Ambient Temperature Commercial (`C' suffix) .................... 0C to +70C Industrial (`I' suffix) ...................... - 40C to +85C Junction Temperature ..................................... +150C Storage Temperature ....................... -65C to +150C Lead Soldering (10 sec max) .......................... +300C
* Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Absolute Maximum Ratings are limited values applied individually while other parameters are within specified operating conditions, and functional operation at any of these conditions is NOT implied. Device performance and reliability may be impaired by exposure to absolute rating conditions for extended periods of time.
RELIABILITY CHARACTERISTICS Symbol
VZAP(1) ILTH(1)(2)
Notes:
Parameter
ESD Susceptibility Latch-Up
Min
2000 100
Max
Units
Volts mA
Test Method
MIL-STD-883, Test Method 3015 JEDEC Standard 17
1. This parameter is tested initially and after a design or process change that affects the parameter. 2. Latch-up protection is provided for stresses up to 100mA on address and data pins from -1V to VCC + 1V.
DC ELECTRICAL CHARACTERISTICS: VDD = +2.7V to +5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified Symbol Parameter Conditions Min Typ Max Units
Resolution 8 ILOAD = 250 nA, TR = C TR = I ILOAD = 1 A, TR = C TR = I ILOAD = 250 nA, TR = C TR = I ILOAD = 1 A, TR = C TR = I VIN = VDD VIN = 0V -- -- -- -- -- -- -- -- -- -- 2 0 2.7 GND -- -- IOH = - 40 A IOL = 1 mA, VDD = +5V IOL = 0.4 mA, VDD = +3V VDD-0.3 -- -- -- 0.6 0.6 1.2 1.2 0.25 0.25 0.5 0.5 -- -- -- -- -- -- 28K 0.5 -- -- -- -- 1 1 -- -- 0.5 0.5 -- -- 10 -10 VDD 0.8 VDD VDD -2.7 -- 1 -- 0.4 0.4 Bits LSB LSB LSB LSB LSB LSB LSB LSB A A V V V V % V V V
Accuracy
INL Integral Linearity Error
DNL
Differential Linearity Error
Logic Inputs
IIH IIL VIH VIL Input Leakage Current Input Leakage Current High Level Input Voltage Low Level Input Voltage VREFH Input Voltage Range VREFL Input Voltage Range VREFH-VREFL Resistance Input Resistance Match High Level Output Voltage Low Level Output Voltage
References
VRH VRL ZIN VIN / RIN VOH VOL
Logic Outputs
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Advanced Information DC ELECTRICAL CHARACTERISTICS (Cont.): VDD = +2.7V to +5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified Symbol
FSO ZSO IL ROUT PSSR TCO TCREF
CAT512
Parameter
Full-Scale Output Voltage Zero-Scale Output Voltage DAC Output Load Current DAC Output Impedance Power Supply Rejection VOUT Temperature Coefficient Temperature Coefficient of VREF Resistance Supply Current (Read) Supply Current (Write) Operating Voltage Range
Conditions
VR = VREFH - VREFL VR = VREFH - VREFL VDD = VREFH = +5V VDD = VREFH = +3V ILOAD = 1 A VDD = +5V, ILOAD = 250nA VREFH= +5V, VREFL = 0V VREFH to VREFL
Min
0.99 VR -- -- -- -- -- -- --
Typ
0.995 VR 0.005 VR -- -- -- -- -- 700
Max
-- 0.01 VR 1 100K 150K 1 200 --
Units
V V A LSB / V V/ C ppm / C
Analog Output
Temperature
Power Supply
IDD1 IDD2 VDD Normal Operating VDD = 5V VDD = 3V -- -- -- 2.7 40 1.2 .6 -- 50 2.0 1.2 5.5 A mA mA V
AC ELECTRICAL CHARACTERISTICS: VDD = +2.7V to +5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified Symbol Digital
tCSMIN tCSS tCSH tDIS tDIH tDO1 tDO0 tHZ tLZ tBUSY tPS tPROG tCLKH tCLKL fC Minimum CS Low Time CS Setup Time CS Hold Time DI Setup Time DI Hold Time Output Delay to 1 Output Delay to 0 Output Delay to High-Z Output Delay to Low-Z Erase/Write Cycle Time PROG Setup Time Minimum Pulse Width Minimum CLK High Time Minimum CLK Low Time Clock Frequency DAC Settling Time to 1 LSB 150 100 0 50 50 -- -- -- -- -- 150 700 500 300 DC -- -- -- -- -- -- -- -- -- -- -- 400 400 4 -- -- -- -- -- 3 6 8 6 -- -- -- -- -- 150 150 -- -- 5 -- -- -- -- 1 10 10 -- -- ns ns ns ns ns ns ns ns ns ms ns ns ns ns MHz s s pF pF
Parameter
Conditions
Min
Typ
Max
Units
CL = 100 pF, see note 1
Analog
tDS CLOAD = 10 pF, VDD = +5V CLOAD = 10 pF, VDD = +3V VIN = 0V, f = 1 MHz(2) VOUT = 0V, f = 1 MHz2)
Pin Capacitance
CIN COUT Input Capacitance Output Capacitance
Notes: 1. All timing measurements are defined at the point of signal crossing VDD / 2. 2. These parameters are periodically sampled and are not 100% tested.
3
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CAT512
A. C. TIMING DIAGRAM
Advanced Information
to
1
2
3
4
5
t CLK H CLK
t CSS CS
t CLK L
t CSH
t CSMIN
t DIS DI t DIH
t LZ DO
t DO0
t HZ t DO1
PROG t PS t PROG RDY/BSY t BUSY
to
1
2
3
4
5
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4
Advanced Information PIN DESCRIPTION Pin
1 2 3 4 5 6 7 8 9 10 11 12 13 14
CAT512
DAC addressing is as follows:
Name
VDD CLK RDY/BSY CS DI DO PROG GND VREFL1 VREFL2 VOUT2 VOUT1 VREFH2 VREFH1
Function
Power supply positive Clock input pin Ready/Busy output Chip select Serial data input pin Serial data output pin EEPROM Programming Enable Input Power supply ground Minimum DAC 1 output voltage Minimum DAC 2 output voltage DAC 2 output DAC 1 output Maximum DAC 2 output voltage Maximum DAC 1 output voltage
DAC OUTPUT VOUT1 VOUT2
A0 0 1
A1 1 1
DEVICE OPERATION The CAT512 is a dual 8-bit Digital to Analog Converter (DAC) whose outputs can be programmed to any one of 256 individual voltage steps. Once programmed, these output settings are retained in non-volatile EEPROM memory and will not be lost when power is removed from the chip. Upon power up the DACs return to the settings stored in EEPROM memory. Each DAC can be written to and read from independently without effecting the output voltage during the read or write cycle. Each output can also be adjusted without altering the stored output setting, which is useful for testing new output settings before storing them in memory. DIGITAL INTERFACE The CAT512 employs a standard 3 wire serial control interface consisting of Clock (CLK), Chip Select (CS) and Data In (DI) inputs. For all operations, address and data are shifted in LSB first. In addition, all digital data must be preceded by a logic "1" as a start bit. The DAC address and data are clocked into the DI pin on the clock's rising edge. When sending multiple blocks of information a minimum of two clock cycles is required between the last block sent and the next start bit. Multiple devices may share a common input data line by selectively activating the CS control of the desired IC. Data Outputs (DO) can also share a common line because the DO pin is Tri-Stated and returns to a high impedance when not in use.
5
CHIP SELECT Chip Select (CS) enables and disables the CAT512's read and write operations. When CS is high data may be read to or from the chip, and the Data Output (DO) pin is active. Data loaded into the DAC control registers will remain in effect until CS goes low. Bringing CS to a logic low returns all DAC outputs to the settings stored in EEPROM memory and switches DO to its high impedance Tri-State mode. Because CS functions like a reset the CS pin has been desensitized with a 30 ns to 90 ns filter circuit to prevent noise spikes from causing unwanted resets and the loss of volatile data. CLOCK The CAT512's clock controls both data flow in and out of the IC and EEPROM memory cell programming. Serial data is shifted into the DI pin and out of the DO pin on the clock's rising edge. While it is not necessary for the clock to be running between data transfers, the clock must be operating in order to write to EEPROM memory, even though the data being saved may already be resident in the DAC control register. No clock is necessary upon system power-up. The CAT512's internal power-on reset circuitry loads data from EEPROM to the DACs without using the external clock.
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CAT512
As data transfers are edge triggered clean clock transitions are necessary to avoid falsely clocking data into the control registers. Standard CMOS and TTL logic families work well in this regard and it is recommended that any mechanical switches used for breadboarding or device evaluation purposes be debounced by a flip-flop or other suitable debouncing circuit. VREF VREF, the voltage applied between pins VREFH &VREFL, sets the DAC's Zero to Full Scale output range where VREFL = Zero and VREFH = Full Scale. VREF can span the full power supply range or just a fraction of it. In typical applications VREFH &VREFL are connected across the power supply rails. When using less than the full supply voltage be mindfull of the limits placed on VREFH and VREFL as specified in the "References" section of DC "Electrical Characteristics". BUSY READY/BUSY When saving data to non-volatile EEPROM memory, the Ready/Busy ouput (RDY/BSY) signals the start and duration of the EEPROM erase/write cycle. Upon receiving a command to store data (PROG goes high) RDY/ BSY goes low and remains low until the programming cycle is complete. During this time the CAT512 will ignore any data appearing at DI and no data will be output on DO. RDY/BSY is internally ANDed with a low voltage detector circuit monitoring VDD. If VDD is below the minimum value required for EEPROM programming, RDY/BSY will remain high following the program command indicating a failure to record the desired data in non-volatile memory. DATA OUTPUT Data is output serially by the CAT512, LSB first, via the Data Out (DO) pin following the reception of a start bit and two address bits by the Data Input (DI). DO becomes active whenever CS goes high and resumes Figure 1. Writing to Memory
to 1 2 3 4 5 6 7 8 9 10 11 12 N N+1 N+2
Advanced Information its high impedance Tri-State mode when CS returns low. Tri-Stating the DO pin allows several 512s to share a single serial data line and simplifies interfacing multiple 512s to a microprocessor. WRITING TO MEMORY Programming the CAT512's EEPROM memory is accomplished through the control signals: Chip Select (CS) and Program (PROG). With CS high, a start bit followed by a two bit DAC address and eight data bits are clocked into the DAC control register via the DI pin. Data enters on the clock's rising edge. The DAC output changes to its new setting on the clock cycle following D7, the last data bit. Programming is accomplished by bringing PROG high sometime after the start bit and at least 150 ns prior to the rising edge of the clock cycle immediately following the D7 bit. Two clock cycles after the D7 bit the DAC control register will be ready to receive the next set of address and data bits. The clock must be kept running throughout the programming cycle. Internal control circuitry takes care of generating and ramping up the programming voltage for data transfer to the EEPROM cells. The CAT512's EEPROM memory cells will endure over 1,000,000 write cycles and will retain data for a minimum of 100 years without being refreshed. READING DATA Each time data is transferred into a DAC control register currently held data is shifted out via the D0 pin, thus in every data transaction a read cycle occurs. Note, however, that the reading process is destructive. Data must be removed from the register in order to be read. Figure 2 depicts a Read Only cycle in which no change occurs in the DAC's output. This feature allows Ps to poll DACs for their current setting without disturbing the output voltage but it assumes that the setting being read is also stored in EEPROM so that it can be restored at the end of the read cycle. In Figure 2 CS returns low before the 13th clock cycle completes. In doing so the EEPROM's Figure 2. Reading from Memory
to 1 2 3 4 5 6 7 8 9 10 11 12
CS NEW DAC DATA DI 1 A0 A1 D0 D1 D2 D3 D4 D5 D6 D7
CS
DI
1
A0
A1 CURRENT DAC DATA
CURRENT DAC DATA DO D0 D1 D2 D3 D4 D5 D6 D7
DO
D0
D1
D2
D3
D4
D5
D6
D7
PROG
PROG
RDY/BSY
RDY/BSY
DAC OUTPUT
CURRENT DAC VALUE NON-VOLATILE
NEW DAC VALUE VOLATILE
NEW DAC VALUE NON-VOLATILE
DAC OUTPUT
CURRENT DAC VALUE NON-VOLATILE
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Advanced Information setting is reloaded into the DAC control register. Since this value is the same as that which had been there previously no change in the DAC's output is noticed. Had the value held in the control register been different from that stored in EEPROM then a change would occur at the read cycle's conclusion. TEMPORARILY CHANGE OUTPUT The CAT512 allows temporary changes in DAC's output to be made without disturbing the settings retained in EEPROM memory. This feature is particularly useful when testing for a new output setting and allows for user adjustment of preset or default values without losing the original factory settings. Figure 3 shows the control and data signals needed to effect a temporary output change. DAC settings may be changed as many times as required and can be made to any of the two DACs in any order or sequence. The temporary setting(s) remain in effect long as CS remains high. When CS returns low all two DACs will return to the output values stored in EEPROM memory. When it is desired to save a new setting acquired using this feature, the new value must be reloaded into the DAC control register prior to programming. This is because the CAT512's internal control circuitry discards from the programming register the new data two clock cycles after receiving it if no PROG signal is received. APPLICATION CIRCUITS
+5V
CAT512
Figure 3. Temporary Change in Output
to 1 2 3 4 5 6 7 8 9 10 11 12 N N+1 N+2
CS
NEW DAC DATA 1 A0 A1 D0 D1 D2 D3 D4 D5 D6 D7
DI
CURRENT DAC DATA DO D0 D1 D2 D3 D4 D5 D6 D7
PROG
RDY/BSY
DAC OUTPUT
CURRENT DAC VALUE NON-VOLATILE
NEW DAC VALUE VOLATILE
CURRENT DAC VALUE NON-VOLATILE
+5V RI
+15V
RF +15V
VDD CONTROL & DATA
VREF H
- +
-15V
VOUT
VDD CONTROL & DATA
VREF H
- +
-15V
VOUT
OPT 505 CAT512
GND VREF L
OP 07
OPT 505 CAT512
GND VREF L
OP 07
VOUT = VDAC
Buffered DAC Output
+5V Vi RI +15V VDD CONTROL & DATA VREF H RF
Amplified DAC Output
DAC INPUT DAC OUTPUT
RF VOUT = (1 + ---) V DAC RI
ANALOG OUTPUT
CODE VDAC = ------ (VFS - VZERO ) + VZERO 255 VFS = 0.99 VREF
V OUT
- +
-15V
MSB 1111
LSB 1111
VZERO = 0.01 VREF 255 ---- (.98 VREF ) + .01 VREF = .990 V REF 255 128 ---- (.98 V ) + .01 V = .502 V REF REF REF 255 127 (.98 V ---- ) + .01 V = .498 V 255 REF REF REF 1 ---- (.98 V ) + .01 V = .014 V 255 REF REF REF 0 ---- (.98 V ) + .01 V = .010 V REF REF REF 255
VREF = 5V R I = RF V OUT = +4.90V V = +0.02V OUT V = -0.02V OUT V = -4.86V OUT V = -4.90V OUT
OPT 505 CAT512
GND VREF L
OP 07
1000
0000 1111 0001
VOUT = VDAC ( R I+ RF) -VI R F RI For R I = RF VOUT = 2VDAC -VI
0111 0000
0000
0000
Bipolar DAC Output 7
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CAT512
APPLICATION CIRCUITS (Cont.)
VREF RC = ---------- 256 * 1 A +5V VREF VREFH Fine adjust gives 1 LSB change in V OFFSET VREF when VOFFSET = ------ 2 127RC
+5V +VREF VREFH
Advanced Information
VDD
VDD
FINE ADJUST DAC
127RC + (+VREF ) - (VOFFSET ) RC = ---------------------- 1 A (-VREF ) + (VOFFSET+ ) Ro = ---------------------- 1 A
FINE ADJUST DAC
+V COARSE ADJUST DAC RC V OFFSET
COARSE ADJUST DAC
RC
+ -
GND
VREF L Ro -VREF VOFFSET
+V
+ -
-V
GND
VREF L
Coarse-Fine Offset Control by Averaging DAC Outputs for Single Power Supply Systems
Coarse-Fine Offset Control by Averaging DAC Outputs for Dual Power Supply Systems
28 - 32V
V+
I > 2 mA
15K 10 F
VDD CONTROL & DATA
VREF H
VREF = 5.000V
VDD
1N5231B
VREF H 5.1V 10K CONTROL & DATA
OPT 505 CAT512
GND VREF L
LT 1029
OPT 505 CAT512
GND VREF L
+ - LM 324
MPT3055EL
OUTPUT 4.02 K 1.00K 10 F 35V 0 - 25V @ 1A
Digitally Trimmed Voltage Reference
Digitally Controlled Voltage Reference
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Advanced Information APPLICATION CIRCUITS (Cont.)
+5V 2.2K VDD VREF 4.7 A
CAT512
LM385-2.5
+15V
ISINK = 2 - 255 mA
DAC
+5V 10K
+ -
10K
2N7000
391W 39 1W
1 mA steps
CONTROL & DATA
CAT512 OPT 505
DAC
+ 2N7000 -
5 A steps
GND
VREF L
5 meg
5 meg
3.9K
10K
10K
- + TIP 30
-15V
Current Sink with 4 Decades of Resolution
+15V
51K
+ TIP 29 -
10K +5V 10K
VDD
VREF H
5 meg
5 meg
39 1W 39 1W
DAC
CONTROL & DATA
-
OPT 505 CAT512
5 meg
+
5 meg
BS170P
1 mA steps
DAC
3.9K
GND
VREF L
- BS170P + LM385-2.5
5 A steps
-15V
ISOURCE = 2 - 255 mA
Current Source with 4 Decades of Resolution
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CAT512
Advanced Information
ORDERING INFORMATION
Prefix CAT Device # 512 Suffix J I -TE13
Optional Company ID
Product Number
Package P: PDIP J: SOIC
2000/Reel
Tape & Reel TE13:
Temperature Range Blank = Commercial (0C to +70C) I = Industrial (-40C to +85C)
Notes: (1) The device used in the above example is a CAT512JI-TE13 (SOIC, Industrial Temperature, Tape & Reel)
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